This course offers detailed training on the Vivado® software tool flow, Xilinx design constraints (XDC), and static timing analysis (STA). Learn to use good FPGA design practices and all FPGA resources to advantage. Learn to fully and appropriately constrain your design by using industry-standard XDC constraints. Learn how the theVivado IDE design database is structured and learn to traverse the design. Create appropriate timing reports to perform full STA and how to appropriately synthesize your design.You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The full FPGA Design Methodology Checklist is also introduced
FPGA designers with intermediate knowledge of HDL and FPGA architecture, and some experience with the Xilinx Vivado Design Suite
Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Vivado software flow; basic FPGA design techniques; basic clock, input, and output timing constraints, and the Constraints Editor
At the end of the comprehensive training, you will have the necessary skills to:
All participants will get the hard copy of the training material and a certificate of participation.
Note: Outstation participants can avail accommodation at an additional cost.
SCO-28, First Floor, Chotti Baradari, Part 1, Garha Road, Jalandhar
+91 99140 77736
+91 81466 07244